Title :
Design of low power differential conditional capturing flip-flop
Author :
Kasiselvanathan, M. ; Saranya, P. ; Lakshmi, A.S. ; Sivasakthi, S.
Author_Institution :
ECE Sri Ramakrishna Eng. Coll., Coimbatore, India
Abstract :
The operation of low/full swing LC resonant clocking scheme helps in reducing the overall power of the system by introducing a modern new flip-flop. The proposed dual mode low/full-swing differential conditional capturing flip-flop (LF-CCFF) operates with a low/full-swing sinusoidal clock through the utilization of reduced swing inverters at the clock port. The LF-CCFF reduces the power consumption compared to the single mode full-swing flip-flop. The power has been obtained by using 180-nm CMOS technology. In addition, a frequency dependent delay associated with driving pulsed flip-flops with a low/full-swing sinusoidal clock has been characterized. The LF-CCFF has compared to the full-swing flip-flop both having the same setup time for a 100 MHz sinusoidal clock.
Keywords :
CMOS logic circuits; flip-flops; logic design; low-power electronics; power consumption; CMOS technology; LC resonant clocking scheme; frequency 100 MHz; low power differential conditional capturing flip-flop; low/full-swing sinusoidal clock; power consumption; size 180 nm; Capacitance; Clocks; Conferences; Flip-flops; Inverters; Power demand; Synchronization; Flip-flop; Full swing; low swing; power;
Conference_Titel :
Current Trends in Engineering and Technology (ICCTET), 2014 2nd International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-7986-8
DOI :
10.1109/ICCTET.2014.6966293
