Title :
A 0.11 μm CMOS clocked comparator for high-speed serial communications
Author :
Okaniwa, Yusuke ; Tamura, H. ; Kibune, Masaya ; Yamazaki, Daisuke ; Cheung, Tszshing ; Ogawa, Junji ; Tzartzanis, Nestoras ; Walker, William W. ; Kuroda, Tadahiro
Author_Institution :
Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan
Abstract :
A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2 V supply was designed and fabricated in 0.11 μm CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10-12 up to 32 Gb/s at a toggle rate of 8 GHz.
Keywords :
CMOS integrated circuits; comparators (circuits); flip-flops; telecommunication equipment; 0.11 μm CMOS clocked comparator; 0.11 micron; 1.2 V; 40 Gbit/s; 8 GHz; clocked buffer; comparator operation; feedback gain switching; front-end sampler; high toggle rate; high-speed serial communications; impedance modulation technique; narrow aperture time; regenerative stage; regenerative stage output buffer; Apertures; Bandwidth; Circuit topology; Clocks; Communication switching; Costs; Impedance; Latches; Output feedback; Signal design;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346558
