Title :
A pixel-parallel image processor for Gabor filtering based on merged analog/digital architecture
Author :
Morie, Takashi ; Umezawa, Jun ; Iwata, Atsushi
Author_Institution :
Kyushu Inst. of Technol., Kitakyushu, Japan
Abstract :
Gabor filtering is a powerful feature extraction method for image recognition. We propose a pixel-parallel processor for Gabor filtering using a newly developed algorithm with nearest-neighbor connections. The LSI has been designed using 0.35 μm CMOS technology based on the merged analog/digital circuit architecture, which uses pulse-width modulation (PWM) signals. The LSI includes 62×71 pixel circuits on a 9.8 mm sq. chip area. Experiments using the fabricated LSI have verified that the spatial frequency of the image is correctly extracted.
Keywords :
CMOS integrated circuits; image recognition; mixed analogue-digital integrated circuits; parallel processing; pulse width modulation; 0.35 micron; CMOS technology; Gabor filtering; image recognition; merged analog/digital architecture; nearest-neighbor connections; pixel-parallel image processor; CMOS technology; Digital filters; Feature extraction; Filtering algorithms; Gabor filters; Image recognition; Large scale integration; Pixel; Pulse width modulation; Signal design;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346563
