Title :
A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs
Author :
Suzuki, H. ; Nishigori, T. ; Yamazaki, T. ; Nakamura, K. ; Oguri, T. ; Atsumo, T. ; Takada, M. ; Ikemoto, A.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A stacked emitter polysilicon (STEP) bipolar technology is described for megabit BiCMOS static RAMs (SRAMs) using TFT (thin film transistor) load cells. The STEP electrode structure consists of the gate (bottom) and the channel (top) polysilicon layers of the TFT. This technology overcomes the perimeter and plug effects for narrow emitter windows. A tungsten-silicide ground line in the RAM cell can be employed to realize a highly stable cell operation at 3.3 V in a 16-Mb BiCMOS SRAM
Keywords :
BiCMOS integrated circuits; SRAM chips; elemental semiconductors; integrated circuit technology; silicon; thin film transistors; 16 Mbit; 3.3 V; BiCMOS SRAMs; STEP electrode structure; TFT load cells; TiSi2-Si; polysilicon bipolar technology; stacked emitter; static RAMs; thin film transistor; BiCMOS integrated circuits; Bipolar transistors; Degradation; Electrodes; Ion implantation; Plugs; Random access memory; Rapid thermal annealing; Thin film transistors; Wiring;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-0727-5
DOI :
10.1109/BIPOL.1992.274074
