A complete stress enhancement model development and verification platform for 32nm technology and beyond

Author

Li, Yanfeng ; Zhu, Nengyong ; Li, Miao ; Wu, Yanjun ; Chen, Qiang ; Cai, Shuang ; Radojcic, Riko ; Nakamoto, Mark

Author_Institution

Accelicon Technol., Inc., Cupertino, CA, USA

fYear

2010

Firstpage

1871

Lastpage

1873

Abstract

Variability from different sources such as layout-dependent effects due to strain has been a main obstacle against aggressive design rules and reducing corner margins in 32nm node and beyond. This paper reports and demonstrates a model development and verification platform to accurately address layout dependences due to strain. This platform has been successfully used in real design exercises at 40nm technology and is being applied for 32nm technology. Test structures and methodologies of developing and verifying stress enhancement models are presented. The platform has been demonstrated to be flexible enough to account for new layout-dependent reliability behavior in strain engineering technologies.

Keywords

SPICE; circuit layout; semiconductor device reliability; semiconductor device testing; stress effects; transistor circuits; SPICE model; layout-dependent reliability behavior; size 32 nm; strain engineering; stress enhancement model development; test structure; transistor performance; verification platform; Analytical models; Data models; Layout; SPICE; Strain; Stress; Transistors; BTI; DFM; SPICE model; TDDB; layout dependences; strained silicon; variability-aware modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667735

Filename

5667735