Title :
A design rule based routing scheme
Author :
Müller, H. ; Mlynsi, D.A.
Author_Institution :
Inst. fuer Theor. Electrotech. und Messtech., Karlsruhe Univ., West Germany
Abstract :
A new approach to the routing problem is presented. Since multilayer routing is provided in nearly all technologies, efficient via handling becomes very important. The proposed routing scheme manages 2 v routing layers (v⩾1), variable wiring width, and variable size of vias. As usual, the method is composed of two steps: global and local routing. However, rectangular routing channels cover the whole chip area and contain pins within. Path calculation is based on a sub-Manhattan metric
Keywords :
VLSI; circuit layout CAD; VLSI; chip area; design rule based routing scheme; efficient via handling; global routing; local routing; multilayer routing; path calculation; pin containing routing channels; rectangular routing channels; routing layers; routing problem; sub-Manhattan metric; variable via size; variable wiring width; Integrated circuit interconnections; Nonhomogeneous media; Pins; Routing; Silicon; Solids; Wire; Wiring; Yttrium;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100497
