A transregional CMOS SRAM with single, logic VDD and dynamic power rails

New circuit techniques are reported that enable a single V_DD SRAM to operate at logic compatible voltages with a cell read current and cell static noise margin (SNM) typically seen with higher/dual V_DD SRAMs. Implemented in a 65nm CMOS SOI process with no alterations to the CMOS process or to a conventional, single V_T SRAM cell, the voltage across power rails of the selected SRAM cells self-biases to permit a higher-than-V_DD voltage during WL active periods and a lower than 2V_T voltage at all other times. Bootstrapping the cell row power supply and regulating the cell subarray virtual ground voltage enables the above ´Transregional´ SRAM operation resulting in near-subthreshold data storage and superthreshold access, lowering total leakage by over 10× and improving I_READ and SNM by 7% and 18% respectively with a total area overhead of less than 13%.