A low power quad phase-locked loop for multiple SerDes standards

This paper presents the design of 0.1-3.6GHz quad phase-locked loop (PLL) for multiple SerDes standards. The PLL has an adaptive bandwidth for different applications. But the bandwidth doesn´t vary with processes and temperatures in every application condition for the process-dependent charge pump current and high precision bandap reference circuit. The core power of the PLL is 6.9mA at 3.125GHz without yielding RMS jitter performance which is about 2.5ps.The active chip area including the biasing is about 0.1mm².