A CMOS analog vector quantizer for pattern recognition

Author

Hung, Yu-Cherng ; Liu, Bin-Da

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

112

Lastpage

115

Abstract

A linear mean-absolute-difference (MAD) cell is designed. Based on this cell and winner-take-all circuit, we propose a parallel analog vector-quantizer for pattern recognition. The experimental circuit is constituted by one input pattern and 16 template patterns with 16 elements. This circuit had been simulated using 0.5 μm CMOS technology by HSPICE. The results show that a pattern can be correctly identified if the difference of the MAD distance metric is larger or smaller than 100 mV. Simulation results demonstrate 250 ns identified time and 16 mW power dissipation for single 3.3 V voltage supply

Keywords

CMOS analogue integrated circuits; SPICE; analogue processing circuits; circuit simulation; neural nets; pattern recognition equipment; vector quantisation; 0.5 micron; 16 mW; 250 ns; 3.3 V; CMOS analog vector quantizer; HSPICE; MAD distance metric; input pattern; linear mean-absolute-difference cell; parallel analog vector-quantizer; pattern recognition; power dissipation; template patterns; winner-take-all circuit; CMOS technology; Circuit simulation; Data compression; Euclidean distance; MOSFETs; Pattern matching; Pattern recognition; Threshold voltage; Vector quantization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824041

Filename

824041