Title :
A 1.5-V 10-b 50 MS/s time-interleaved switched-opamp pipeline CMOS ADC with high energy efficiency
Author :
Vaz, Bruno ; Goes, João ; Paulino, Nuno
Author_Institution :
Campus da Faculdade de Cie ncias e Tecnologia, UNINOVA-CRI, Monte Da Caparica, Portugal
Abstract :
A 1.5V 10-b 50MS/s 2-channel pipeline ADC is described. Amplifiers arc efficiently shared between channels using low-voltage techniques to reduce the power supply. The selected resolution per stage avoids the need of scaling the stages, simplifying the implementation of a low-power design. Measurements from the prototypes fabricated in a 0.18 μm CMOS technology exhibit 10b DNL, 9.5b INL and 9.2 effective bits at Nyquist-rate. The chip occupies 1.3 mm2 and dissipates only 29 mW at 1.5V.
Keywords :
CMOS integrated circuits; analogue-digital conversion; operational amplifiers; 0.18 micron; 1.5 V; 29 mW; Nyquist-rate; high energy efficiency; low-voltage techniques; power supply; selected resolution per stage; time-interleaved switched-opamp pipeline CMOS ADC; CMOS technology; Design optimization; Energy efficiency; Pipelines; Power dissipation; Power measurement; Power supplies; Semiconductor device measurement; Switching circuits; Voltage;
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
DOI :
10.1109/VLSIC.2004.1346640
