DocumentCode :
1640944
Title :
Step by step placement strategies for building block layout
Author :
Onodera, H. ; Sakamoto, M. ; Kurihara, T. ; Tamaru, K.
Author_Institution :
Dept. of Electron., Kyoto Univ., Japan
fYear :
1989
Firstpage :
921
Abstract :
A set of placement algorithms is presented for building-block layout that evolves a solution step by step in a three-stage process. The first stage produces global placement using a novel force model which reflects not only the connectivity but also the dimensions of the blocks. The second stage improves the degree of the shape matching by shift compaction, a recently developed pseudo-two-dimensional compaction method. The third stage adjusts the spacing of the placement considering the actual routing path for each net. The algorithms treat all blocks simultaneously and explore a solution effectively first on a global level and later in detail. An example with 33 blocks and 123 nets is given to demonstrate the performance in which the amount of space that is occupied neither by the blocks nor the routing channels is estimated to be as small as 9% of the overall placement area
Keywords :
circuit layout CAD; block connectivity; block dimensions; building-block layout; global placement; net routing path considerations; novel force model; overall placement area; placement algorithms; placement spacing; pseudo-two-dimensional compaction method; routing channels; shift compaction shape matching; simultaneous block treatment; step by step placement algorithms; three-stage process; Minimization methods; Routing; Shape;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
Type :
conf
DOI :
10.1109/ISCAS.1989.100502
Filename :
100502
Link To Document :
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