Title :
A 2-locking-cycle skew-compensation circuit with the capability of tracking runtime-variations
Author :
Cheng, Chun-Yuan ; Wang, Jinn-Shyan ; Chien, Yung-Chen ; Wang, Yi-Ming
Author_Institution :
Dept. of EE, Nat´´l Chung-Cheng Univ., Taiwan
Abstract :
The open-loop de-skewing circuits are traditionally used for fast clock synchronization, but they are unable to deal with the problems induced by run-time variations. This paper presents the design of a skew compensation circuit that can achieve fast lock-in and also perform maintenance operation after lock-in. This circuit is designed on top of the open-loop half-delay-line skew compensation circuit (HDSC) to get a lock-in time of two cycles, and extra circuits are added for monitoring the influence of runtime temperature and supply-voltage variations and maintaining the de-skewing effect.
Keywords :
logic circuits; logic design; 2-locking-cycle skew-compensation circuit; HDSC; half-delay-line skew compensation circuit; open-loop de-skewing circuit; runtime temperature; supply-voltage variation; Clocks; Delay; Detectors; Monitoring; Synchronization; System-on-a-chip; Temperature sensors;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667809
