FPGA Implementation of a Wireless Modem Suitable for Digital Satellite News Gathering

In this paper, a prototype design for a wireless modem suitable for digital satellite news gathering is presented. The implementation aspects of a two-stage Pragmatic TCM codec into a Xilinx Virtex-II FPGA are addressed. The main design challenge is to implement the algorithm from a high abstract-level down to an actual circuitry, using the Xilinx system generator for DSP. This tool provides high-level abstractions that are automatically compiled into an FPGA, with no loss in performance over designs implemented in lower-level languages [7]. The system includes concatenated FEC codes, interleaver/de- interleaver and SQRC digital filters. The design flow demonstrates an approach to implement and prototype real-time base band modem into a programmable chip. The modem is efficiently implemented into 0.15 mum/0.12 mum CMOS 8-layer metal process Virtex II FPGA. Finally, the resulting circuitry is simulated and confirmed to transmit/receive digital audio and video signals up to 27.778 Mbit/s.