A memory access system for merged memory with logic LSIs

Author

Kim, Youngsik ; Han, Tack-Don ; Kim, Shin-Dug

Author_Institution

Dept. of Comput. Sci., Yonsei Univ., Seoul, South Korea

fYear

1999

fDate

6/21/1905 12:00:00 AM

Firstpage

384

Lastpage

387

Abstract

This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM´s by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications

Keywords

DRAM chips; integrated logic circuits; large scale integration; memory architecture; CPI; DRAM architecture; cache refill time; delayed precharge scheme; execution-driven simulation; memory access control; merged memory with logic LSI; multiple block access; page hit ratio; Access control; Bandwidth; Computer architecture; Computer science; Delay effects; Energy consumption; Large scale integration; Logic; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on

Conference_Location

Seoul

Print_ISBN

0-7803-5705-1

Type

conf

DOI

10.1109/APASIC.1999.824114

Filename

824114

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1642292