Title :
Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling
Author :
Song, Ki-Whan ; Kyung, Kye-Hyun ; Kim, Chang-Hyun
Author_Institution :
DRAM Design, Samsung Electron. Co. Ltd., Kyungki, South Korea
fDate :
6/21/1905 12:00:00 AM
Abstract :
This paper describes a methodology to analyze a long periodic channel. The work was performed for the RAMBUS system. The analysis is focused on DRAM loading effects on electrical signal integrity. We suggest some proper windows of DRAM input impedance for 800 MHz signaling. Without additional constraints to ΔLin (pin-to-pin Lin differences), the skew amounts to 45 ps, which can be lowered to 22 ps by the control of ΔLin within 1.5 nH
Keywords :
DRAM chips; electric impedance; memory architecture; transmission line theory; 800 MHz; 800 MHz signaling; DRAM input impedance; DRAM loading effects; RAMBUS system; data bus; electrical signal integrity; long periodic channel analysis methodology; optimum windows; pin-to-pin inductor differences; skew; Attenuation; Bandwidth; Degradation; Frequency; Impedance; Partial differential equations; Random access memory; Signal analysis; Timing; Transmission lines;
Conference_Titel :
ASICs, 1999. AP-ASIC '99. The First IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-5705-1
DOI :
10.1109/APASIC.1999.824122
