Design and FPGA implementation of block synchronizer for Viterbi decoder

Block synchronizer plays vital role in proper functioning of Viterbi decoder as it provides the required phase and node synchronized data to Viterbi decoder. The paper presents, application and implementation of syndrome based block synchronizer for Binary Phase Shift Keying (BPSK) system and ½ code rates. The developed method is hardware efficient and does not require Viterbi decoder for decision, as the case with the other methods, therefore suitable for high speed applications. Different cases for node and phase synchronizations are evolved and system is tested both at algorithm and implementation level for that. The design is coded in VHDL and targeted to Xilinx xc4vsx35-10ff668 FPGA. Real time testing is carried out by interfacing the block synchronizer with Hard/Soft Viterbi decoder. Test results are in line with simulation results and performance of algorithm is found to be satisfactory.