Title :
Performance elements for 28nm gate length bulk devices with gate first high-k metal gate
Author :
Yuan, J. ; Gruensfelder, C. ; Lim, K.Y. ; Wallner, T. ; Jung, M.K. ; Sherony, M.J. ; Lee, Y.M. ; Chen, J. ; Lai, C.W. ; Chow, Y.T. ; Stein, K. ; Song, L.Y. ; Onoda, H. ; An, C.W. ; Wang, H. ; Moon, B.K. ; Kim, J. ; Inokuma, H. ; Yamasaki, H. ; Shah, J. ;
Author_Institution :
Semicond. R&D Center, IBM, Hopewell junction, NY, USA
Abstract :
In this paper, we describe the performance elements used in our 28nm bulk devices with the gate first high-k/metal gate scheme for high performance applications. By using the innovative stressor integrations including improved stress memory technique (SMT), optimized embedded SiGe process and dual stress liner, Ieff of ~540/360 uA/um have been obtained for NMOS and PMOS respectively with the gate length of 28nm and pitch of 113.4nm (Ioff =100 nA/um, Vdd=0.85V). Good Vth mis-match (Avt of ~2.4 mV-um) has been achieved for SRAM devices with the high-k/metal gate, signal-noise-ratio of ~0.2V has been demonstrated in the high performance SRAM cell (0.152 um2) with Vdd of 0.85V.
Keywords :
Ge-Si alloys; MOSFET; SRAM chips; high-k dielectric thin films; stress effects; NMOS; PMOS; SRAM device; SiGe; dual stress liner; gate first high-k metal gate; gate length bulk device; high performance application; signal-noise-ratio; size 28 nm; stress memory; stressor integration; High K dielectric materials; Logic gates; MOS devices; Metals; Performance evaluation; Random access memory; Stress;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667851
