Title :
Soft error considerations for deep-submicron CMOS circuit applications
Author :
Cohen, N. ; Sriram, T.S. ; Leland, N. ; Moyer, D. ; Butler, S. ; Flatley, R.
Author_Institution :
Alpha Semicond. Technol. Group, Compaq Comput. Corp., Houston, TX, USA
Abstract :
The increasing importance of characterizing both memory arrays and core logic when estimating soft error FIT (failure in time) rates has been demonstrated using test-circuits, a 21264 Alpha microprocessor, and simulations. The reduction of operating voltage has been determined to increase the soft error rate exponentially at 2.1-2.2 decades/volt. Based on the SIA roadmap for CMOS scaling trends, meeting FIT rate requirements in the core logic will pose many challenges in the imminent future.
Keywords :
CMOS digital integrated circuits; errors; failure analysis; integrated circuit reliability; microprocessor chips; Alpha microprocessor; core logic; deep submicron CMOS circuit; failure in time rate; memory array; soft error; CMOS logic circuits; CMOS technology; Circuit testing; Computer errors; Logic arrays; Logic design; Logic testing; Microprocessors; Performance evaluation; Voltage;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824159
