Iterative detection/decoding of majority-logic decodable nonbinary LDPC codes over partial response channels

This paper is concerned with the applications of majority-logic decodable nonbinary low-density parity-check (LDPC) codes to partial response (PR) channels. We propose a joint detection/decoding algorithm that works in an iterative manner by exchanging messages between the Viterbi detector and a generalized majority logic decoder (GMLGD). The Viterbi detector is implemented over a sectionalized trellis. The hard-decisions made by the Viterbi detector are then passed to the decoder. The decoder delivers as output estimates of each coded symbols, which will be utilized in next iteration to update the branch metrics of the trellis. Since the proposed algorithm requires only integer operations and finite field operations, it can be implemented with simple combinational logic circuits. Simulation results and complexity analysis show that, when compared with the conventional turbo equalizer implemented with the BCJR algorithm and the Q-ary sum-product algorithm (BCJR-QSPA), the proposed algorithm has a much lower complexity but suffers from a little performance degradation. So the proposed algorithm provides a good candidate for trade-offs between performance and complexity.