A 10b 100MS/s 25.2mW 0.18μm CMOS ADC with various circuit sharing techniques

This work describes a 10 b 100 MS/s 0.18 μm CMOS three-stage pipeline ADC. Two MDACs share an op-amp without MOS switches connected in series while removing a memory effect. Three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC with an active die area of 0.80 mm² shows DNL and INL within 0.58LSB and 0.94LSB, respectively, and consumes 25.2 mW at 1.8 V and 100 MS/s.