Title :
Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs
Author :
Wong, Si-Seng ; Zhu, Yan ; Chan, Chi-Hang ; Chio, U-Fat ; Sin, Sai-Weng ; Seng-Pan U ; Martins, R.P.
Author_Institution :
Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao, China
Abstract :
A calibration technique is proposed to apply for split capacitor array of successive approximation register (SAR) ADC. This technique calibrates the parasitic effects of the split capacitor array by two-step ratio approaching technique, and achieves medium-to-high resolution. The calibration technique is designed and simulated under a 10-bit 100 MS/s SAR ADC structure, with 15% to 25% of top plate parasitic capacitance. The simulation results show that the proposed technique can improve the THD from -41 dB to -59 dB at Nyquist input frequency for the worst case. The DNL/INL is improved from 5.02/5.6 LSB to 0.25/0.38 LSB, respectively.
Keywords :
analogue-digital conversion; calibration; capacitors; SAR ADC; parasitic calibration; split capacitor array; successive approximation register; two step ratio approaching technique; Attenuation; Calibration; Capacitors; Laboratories; Linearity; Logic arrays; Parasitic capacitance; Silicon compounds; Very large scale integration; Voltage; analog-to-digital converter (ADC); offset calibration; parasitic calibration; split capacitor array; sucessive approximation register (SAR);
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423780