Title :
On-chip interconnect evaluation on delay time increase by crosstalk
Author :
Yamashita, K. ; Odanaka, S. ; Egashira, K. ; Ueda, T.
Author_Institution :
ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan
Abstract :
This paper describes on-chip interconnect evaluation on the delay time increase by crosstalk. The new test configurations were applied to evaluate the impact of low-k materials and improved circuit techniques on the delay time increase by crosstalk. It is found that the reduction of Cl for low-k materials, organic and air gap, is effective in reducing the delay time increase by crosstalk. Also, it is experimentally verified that improved circuit techniques such as repeaters and variable pitch routers significantly reduce not only interconnect delay but also delay time increase by crosstalk.
Keywords :
CMOS integrated circuits; crosstalk; delays; dielectric thin films; integrated circuit interconnections; integrated circuit noise; integrated circuit testing; organic compounds; 0.18 /spl mu/m CMOS process; 0.18 mum; Al; air gap materials; circuit techniques; crosstalk; delay time increase; interconnect delay; low-k materials; on-chip interconnect evaluation; organic materials; repeaters; ring oscillator; test configurations; two level Al; variable pitch routers; Circuit testing; Crosstalk; Delay effects; Integrated circuit interconnections; Inverters; Materials testing; Repeaters; Ring oscillators; Semiconductor device noise; Wire;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.824232
