A high performance 36V complementary bipolar technology on low thermal resistance compound buried layer SOI substrates

Author

Harrington, S.J. ; Bousquet, A. ; Nigrin, S. ; Suder, S. ; Armstrong, B.M.

Author_Institution

Plessey Semicond., Swindon, UK

fYear

2010

Firstpage

37

Lastpage

40

Abstract

In this paper a new high voltage, high performance, high packing density, silicon complementary bipolar technology on novel low thermal resistance compound buried layer (CBL) SOI is reported. NPN and Vertical PNP devices have been fabricated with matched DC and AC characteristics, cut-off frequencies of 3 GHz and breakdowns greater than 36 Volts. The thermal resistance and substrate capacitance of the fabricated devices confirms the superior performance of the CBL SOI substrates.

Keywords

bipolar transistors; buried layers; semiconductor device breakdown; semiconductor device manufacture; silicon-on-insulator; thermal resistance; MIS capacitors; NPN devices; bipolar technology; bipolar transistors; frequency 3 GHz; low thermal resistance compound buried layer SOI substrates; semiconductor device breakdown; semiconductor device manufacture; substrate capacitance; vertical PNP devices; voltage 36 V; Capacitance; Silicon; Silicon on insulator technology; Substrates; Thermal resistance; Transistors; Bipolar transistors; Complementary circuits; MIS capacitors; Semiconductor device breakdown; Semiconductor device manufacture; Semiconductor device thermal factors; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2010 IEEE

Conference_Location

Austin, TX

ISSN

1088-9299

Print_ISBN

978-1-4244-8578-9

Type

conf

DOI

10.1109/BIPOL.2010.5667978

Filename

5667978