Title :
Symbolic compaction of digital CMOS cells
Author :
Barzaghi, M. ; Curatelli, F. ; Caviglia, D.D. ; Bisio, G.M.
Author_Institution :
DIBE, Genova Univ., Italy
Abstract :
A symbolic compaction program intended for the generation of CMOS digital cells is described. This program also performs jog insertion to improve the layout compaction and makes an estimation of the propagation delay. The compaction data structure and algorithms implemented are discussed. The jog inserter and the delay evaluation are described, and results are reported
Keywords :
CMOS integrated circuits; circuit layout CAD; data structures; delays; digital integrated circuits; CAD; compaction data structure; delay evaluation; digital CMOS cells; jog insertion; layout compaction; propagation delay; symbolic compaction program; CMOS digital integrated circuits; CMOS technology; Compaction; Data structures; Delay estimation; Design automation; Digital circuits; Manuals; Propagation delay; Wires;
Conference_Titel :
Electrotechnical Conference, 1991. Proceedings., 6th Mediterranean
Conference_Location :
LJubljana
Print_ISBN :
0-87942-655-1
DOI :
10.1109/MELCON.1991.161817
