Title :
On-chip transaction level debug support for system-on-chips
Author :
Gharehbaghi, Amir Masoud ; Fujita, Masahiro
Author_Institution :
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper introduces a method to raise the debug abstraction level of communications to transaction level in post-silicon verification. The method is based on on-chip instrumentation using formal specifications of the on-chip bus communication protocols. Furthermore, we present a method for automatic analysis of extracted transactions to find potential erroneous transaction sequences. The post analysis method searches for certain patterns to find potential problems such as deadlock and race. To show the feasibility of the method, it is applied to a number of on chip buses. It is shown that the area overhead of the method is very low and it is effective to locate bugs.
Keywords :
formal specification; program debugging; protocols; system buses; system-on-chip; chip buses; formal specification; on-chip bus communication protocol; on-chip instrumentation; on-chip transaction level debug support; post-silicon verification; system-on-chips; transaction sequences; Computer bugs; Debugging; Educational technology; Formal specifications; Hardware; Pattern analysis; Protocols; System recovery; System-on-a-chip; Very large scale integration; post-silicon debug; system-on-a-chip (SoC); transaction level debug;
Conference_Titel :
SoC Design Conference (ISOCC), 2009 International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-5034-3
Electronic_ISBN :
978-1-4244-5035-0
DOI :
10.1109/SOCDC.2009.5423891
