A VLSI implementation of a frequency synthesizer based on a charge pump PLL

Author

Bozomitu, R.G. ; Cehan, V. ; Barabasa, C. ; Cojan, N.

Author_Institution

Telecommun. & Inf. Technol., “Gheorghe Asachi” Tech. Univ., Iaşi, Romania

fYear

2014

fDate

23-26 Oct. 2014

Firstpage

141

Lastpage

144

Abstract

The paper presents a VLSI implementation of a frequency synthesizer based on a charge pump PLL. Indirect synthesis uses a Phase Lock Loop (PLL) architecture with a programmable frequency divider in the loop, providing a large number of frequencies from a single reference frequency. The proposed frequency synthesizer is designed for Short Range Device (SRD) applications around 433MHz and for FM radio in the (88-108)MHz frequency band. The simulations were performed in 0.18μm CMOS technology and confirm the theoretically obtained results.

Keywords

CMOS logic circuits; VLSI; charge pump circuits; frequency dividers; frequency synthesizers; logic design; phase locked loops; CMOS technology; VLSI implementation; charge pump PLL; frequency 88 MHz to 108 MHz; frequency synthesizer; indirect synthesis; phase lock loop architecture; programmable frequency divider; reference frequency; short range device applications; size 0.18 mum; Charge pumps; Frequency conversion; Frequency synthesizers; Integrated circuit modeling; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; CMOS; PLL; SRD; charge-pump; frequency synthesizer;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Technology in Electronic Packaging (SIITME), 2014 IEEE 20th International Symposium for

Conference_Location

Bucharest

Type

conf

DOI

10.1109/SIITME.2014.6967012

Filename

6967012