Title :
MSXmin: a self-routing multicast ATM packet switch with O(log2 N) delay and O(N log2N) hardware complexity
Author :
Kannan, Rajgopal ; Ray, Sibabrata
Author_Institution :
Dept. of Comput. & Inf. Sci., Michigan Univ., Dearborn, MI, USA
Abstract :
We propose and analyze the architecture for a large scale high-speed multicast switch called MSXmin. The hardware complexity of MSXmin is O(Nlog2N) which compares favorably with existing architectures. Further, the internal latency of the MSXmin is O(log2N) bits. While it is superior to the existing architectures in terms of the hardware complexity and the internal latency, it is comparable to other multicast switches in terms of the header overhead and translation table complexity. MSXmin is output buffered and based on the group knockout principle. Moreover, MSXmin is a dual-bit controlled tree-based switch
Keywords :
asynchronous transfer mode; buffer storage; computational complexity; delays; large-scale systems; multistage interconnection networks; packet switching; telecommunication network routing; Banyan network; MSXmin; delay; dual-bit controlled tree-based switch; group knockout principle; hardware complexity; header overhead; internal latency; large scale high-speed switch architecture; output buffered switch; self-routing multicast ATM packet switch; translation table complexity; Asynchronous transfer mode; Computer architecture; Costs; Delay; Hardware; Large-scale systems; Packet switching; Routing; Switches; Unicast;
Conference_Titel :
Global Telecommunications Conference, 1997. GLOBECOM '97., IEEE
Conference_Location :
Phoenix, AZ
Print_ISBN :
0-7803-4198-8
DOI :
10.1109/GLOCOM.1997.632542
