FPGA-based single precision iterative floating point multiplier for educational use

An iterative, single precision, floating point multiplier is described in this paper, designed and verified using the Verilog description language. The design is provided for educational use, complementing the practical activity in Computer Architecture related courses. The area overhead of the architecture is reduced by resorting to shift-and-add multiplication, allowing to conveniently storing the mantissa result on the required number of bits while facilitating the management of the rounding bits. The architecture was designed as a case study for different adder configuration as well as various sequential binary multiplication procedures.