DocumentCode :
1648030
Title :
Distance-Guided Hybrid Verification with GUIDO
Author :
Bertacco, Valeria
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI
fYear :
2006
Firstpage :
151
Lastpage :
151
Abstract :
Summary form only given. Constrained random simulation is a widespread technique used to perform functional verification of complex digital designs, because it can generate simulation vectors at a very high rate. However, the generation of high-coverage tests remains a major challenge even in light of this high performance. On the other hand, formal verification solutions can deliver very high confidence in the correctness of a design, but they are very limited in the complexity of the designs that they can tackle. In this talk we present Guido, a novel hybrid solution to boost the coverage achieved during functional verification by closely integrating simulation-based and formal techniques. Guido exploits formal verification to effectively guide a logic simulation towards a verification or coverage goal of interest. Guido provides significant value to a verification engineer because 1) it guides the simulation by means of a distance function derived from the circuit structure, and 2) it has a trace sequence controller which monitors and controls the direction of the simulation by striking a balance between random chance and controlled hill-climbing. Finally, we present experimental results indicating that Guido can tackle the verification of complex designs, including a picoJava microprocessor, and reach a verification goal in far fewer simulation cycles than constrained random simulation
Keywords :
formal verification; logic simulation; Guido; complex digital design functional verification; constrained random simulation; controlled hill-climbing; design correctness; distance function; distance-guided hybrid verification; formal functional verification; high-coverage test; logic simulation guide; random chance hill-climbing; simulation direction control; simulation direction monitoring; simulation vector generation; simulation-based technique; trace sequence controller; Circuit simulation; Computational modeling; Computer industry; Computer simulation; Conferences; Formal verification; Gas insulated transmission lines; Hardware design languages; Performance evaluation; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High-Level Design Validation and Test Workshop, 2006. Eleventh Annual IEEE International
Conference_Location :
Monterey, CA
ISSN :
1552-6674
Print_ISBN :
1-4244-0680-3
Electronic_ISBN :
1552-6674
Type :
conf
DOI :
10.1109/HLDVT.2006.319979
Filename :
4110078
Link To Document :
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