A general expansion architecture for large-scale multicast ATM switches

This paper proposes a multicast universal multistage interconnection network (multicast UniMIN) switch architecture for constructing large-scale multicast ATM switches with any type of small multicast switch. The proposed architecture consists of a buffered distribution network that can perform cell routing and replication simultaneously, and a column of output switch modules (OSMs). The adoption of channel grouping and virtual first-in-first-out (FIFO) buffers results in a high delay/throughput performance, and the distributed lookup table scheme for multicast addressing greatly reduces the size of a single lookup table. Analytical and simulation results show that high delay/throughput performance is obtained for both unicast and multicast traffic, and the proposed architecture yields an even better performance for multicast traffic than for unicast traffic. In addition, the multicast UniMIN switch has such good features such as modular expandability, simple hardware, and no internal speed-up operation