Design and reliability of a micro-relay technology for zero-standby-power digital logic applications

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V_DD) to be scaled down further than for CMOS devices. This paper describes design techniques to achieve reliable (high-endurance) MEM relay operation. Prototype relays fabricated using a CMOS-compatible process are demonstrated to operate with low surface adhesion force, adequately low on-state resistance (< 100 k¿) over a wide temperature range (20°C-200°C), and >10⁹ on/off switching cycles in N₂ ambient without stiction- or welding-induced failure. Measured characteristics are well predicted by both ANSYS simulations and an analytical model. Using the calibrated analytical model, scaled relay technology is projected to achieve >10× energy savings over comparably sized CMOS technology at throughputs up to ~100 MHz.