Title :
A neural network integrated circuit utilizing programmable threshold voltage devices
Author :
Borgstrom, Tom ; Bibyk, Steve
Author_Institution :
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
Abstract :
A reconfigurable neural network architecture suitable for CMOS VLSI fabrication is introduced. Essential elements of this architecture, including a novel and compact programmable synaptic element and a summing/thresholding amplifier, are presented and analyzed. The progress made towards the fabrication of this design by the MOSIS 2-μm, double-poly, p-well process is discussed
Keywords :
CMOS integrated circuits; VLSI; computer architecture; neural nets; 2 micron; CMOS VLSI fabrication; MOSIS; double-poly p-well process; neural network integrated circuit; programmable synaptic element; programmable threshold voltage devices; summing/thresholding amplifier; Circuits; Dielectric devices; Electron traps; Fabrication; Multilayer perceptrons; Neural networks; Neurons; Pulse amplifiers; Threshold voltage; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100576
