Title :
VMR: VLSI-compatible metallic carbon nanotube removal for imperfection-immune cascaded multi-stage digital logic circuits using Carbon Nanotube FETs
Author :
Patil, Nishant ; Lin, Albert ; Zhang, Jie ; Wei, Hai ; Anderson, Kyle ; Wong, H. S Philip ; Mitra, Subhasish
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
Metallic carbon nanotubes (CNTs) create source-drain shorts in Carbon Nanotube Field Effect Transistors (CNFETs) resulting in excessive leakage (Ion/Ioff < 5) and highly degraded noise margins. A new technique, VLSI-compatible Metallic-CNT Removal (VMR), overcomes metallic CNT challenges by combining layout design with CNFET processing. VMR produces CNFET circuits with Ion/Ioff in the range of 103-105, and overcomes the limitations of existing metallic-CNT removal techniques. VMR enables first experimental demonstration of complex cascaded CNFET logic circuits. Such logic circuits are immune to both mis-positioned and metallic CNTs.
Keywords :
VLSI; carbon nanotubes; cascade networks; insulated gate field effect transistors; logic circuits; logic design; nanotube devices; C; VLSI-compatible metallic carbon nanotube removal; VMR; carbon nanotube field effect transistors; complex cascaded CNFET logic circuits; degraded noise margins; excessive leakage; imperfection-immune cascaded multistage digital logic circuits; layout design; metallic carbon nanotubes; Breakdown voltage; CNTFETs; Carbon nanotubes; Degradation; Electric breakdown; Electrodes; Etching; Logic circuits; Semiconductivity; Very large scale integration;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424295
