Title :
Design issues and possible solutions for low-cost and high-efficiency LSIs
Author :
Mizuno, Masayuki
Author_Institution :
Device Platforms Res. Labs., NEC Corp., Kanagawa, Japan
Abstract :
Large scale integration with advanced CMOS technologies has been reducing cost, but maintaining chip dependability is becoming more and more difficult. This is due to increasing complexity of system design and increasing uncertainty of signal timing and level. Chip dependability can be realized at low cost and maintain high efficiency by combining technologies of (A) ¿Never produce defects¿ during chip design and manufacturing, (B) ¿Never let defects escape¿ during chip testing, and (C) ¿Never let defects lead to failure¿ during operations, as shown in Fig. 1.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit testing; large scale integration; CMOS technologies; chip testing; high-efficiency LSI; low-cost LSI; signal timing; CMOS technology; Chip scale packaging; Circuit testing; Costs; Flexible manufacturing systems; Large scale integration; Logic design; Logic testing; Network-on-a-chip; Timing;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424327
