DocumentCode :
1652168
Title :
Engineering the complete MANOS-type NVM stack for best in class retention performance
Author :
Gilmer, D.C. ; Goel, N. ; Park, H. ; Park, C. ; Verma, S. ; Bersuker, G. ; Lysaght, P. ; Tseng, H.-H. ; Kirsch, P.D. ; Saraswat, K.C. ; Jammy, R.
Author_Institution :
SEMATECH, Austin, TX, USA
fYear :
2009
Firstpage :
1
Lastpage :
4
Abstract :
We demonstrate best in class performance for MANOS-type charge-trap flash non-volatile memory devices through improved program/erase (P/E), endurance and retention. Band-engineered (BE) tunnel-oxides (TO) and BE-SiNx charge-trap layers are employed to optimize program, erase, and endurance with trade-off in retention. However, for the 1st time we combine BE-TO, BE-SiNx, BE-blocking layer (BE-BL) and an oxygen-bearing high effective-work-function (EWF) electrode to dramatically improve retention while maintaining the combined benefits from the engineering of each individual stack component. Resulting device improvements include larger ¿Vth P/E windows of > 300%, enduring P/E cycles to at least 100 K cycles while maintaining a window > 4 V, and retention approaching zero% charge loss over 24 hours at 150°C. The large, enduring windows with improved retention are favorable for multi-level cell application beyond the 30 nm node.
Keywords :
flash memories; random-access storage; silicon compounds; BE-SiNx; BE-TO; BE-blocking layer; MANOS-type NVM stack; band-engineered tunnel-oxide; charge-trap flash non-volatile memory device; class retention performance; effective-work-function electrode; temperature 150 C; Aluminum oxide; Electrodes; Electronic mail; Jamming; MOSFETs; Maintenance engineering; Nonvolatile memory; Stress; Thickness control; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
Type :
conf
DOI :
10.1109/IEDM.2009.5424331
Filename :
5424331
Link To Document :
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