DocumentCode :
1652828
Title :
Hardware synthesis for multi-dimensional time
Author :
Guillou, Anne-Claire ; Quinton, Patrice ; Risset, Tanguy
Author_Institution :
IRISA, Rennes, France
fYear :
2003
Firstpage :
40
Lastpage :
50
Abstract :
We introduce some basic principles for extending the classical systolic synthesis methodology to multidimensional time. Multidimensional scheduling enables complex algorithms that do not admit linear schedules to be parallelized, but it also requires the use of memories in the architecture. We explain how to obtain compatible allocation and memory functions for VLSI (or SIMD-like code) generation. We also present an original mechanism for controlling a VLSI architecture that has a multidimensional schedule. A structural VHDL code has been derived and synthesized (for implementation on FPGA platforms) using these systematic design principles. These results are preliminary steps to the hardware synthesis for multidimensional time.
Keywords :
VLSI; field programmable gate arrays; hardware description languages; hardware-software codesign; memory architecture; parallel programming; processor scheduling; resource allocation; systolic arrays; FPGA; VLSI; high-level hardware synthesis; multi-dimensional time; multidimensional scheduling; systolic architecture; Algorithm design and analysis; Control system synthesis; Difference equations; Field programmable gate arrays; Hardware; Partitioning algorithms; Prototypes; Scheduling algorithm; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2003. Proceedings. IEEE International Conference on
ISSN :
2160-0511
Print_ISBN :
0-7695-1992-X
Type :
conf
DOI :
10.1109/ASAP.2003.1212828
Filename :
1212828
Link To Document :
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