DocumentCode :
1655290
Title :
Enhanced technique for built-in self-test of sequential logic
Author :
Chien, Benedict ; Simmons, Stan
Author_Institution :
Dept. of Electr. & Comput. Eng., Queen´´s Univ., Kingston, Ont., Canada
Volume :
4
fYear :
2004
Firstpage :
2009
Abstract :
A modified circular self-testing technique based on circular self test path (CSTP) is presented. While the original CSTP technique offered advantages such as low area overhead and simple control logic, the fault coverage achieved may be limited due to limit cycling and register adjacency issues. This paper presents a modification to CSTP, called flushing, to minimize the chances of limit cycles and also reduce the effects of register adjacency issues on the fault coverage. Results indicate that in many cases, flushing can increase fault coverage and prevent limit cycling in circuits with a low number of flip flops.
Keywords :
built-in self test; flip-flops; limit cycles; logic testing; sequential circuits; CSTP; built-in self-test; circular self test path; fault coverage; flip flops; flushing; limit cycles; limit cycling; register adjacency; sequential logic; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Flip-flops; Logic circuits; Logic testing; Registers; Sequential analysis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 2004. Canadian Conference on
ISSN :
0840-7789
Print_ISBN :
0-7803-8253-6
Type :
conf
DOI :
10.1109/CCECE.2004.1347628
Filename :
1347628
Link To Document :
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