Low-level run-time reconfiguration of FPGAs for dynamic environments

In this paper, we build on the ongoing project of reconfigurable learning techniques in autonomous agents, by taking a look at the run-time reconfiguration of on-board digital hardware resources, such as a field-programmable gate array (FPGA). The advent of such reconfigurable devices has allowed for a revolutionary type of computing, mainly reconfigurable computing (RC). This work extends the research first presented in Voicu et al. (2002). The main goal of this project is to abstract the physical resources in order to provide the higher-level tasks with a consistent application programming interface (API), that can be utilized to run-time reconfigure (RTR) the FPGA. The outlined goal is broken into the three following objectives: modeling the FPGA resources, running a placement algorithm for the various hardware blocks (HB) and managing the physical resources of the FPGA. The aforementioned have been implemented and tested using the Xilinx JBits API, which is a development framework for Xilinx FPGA based on the Java language. A graphical user interface (GUI), which hooks into the JBits BoardScope class, has been designed and realized, showcasing the entire RTR API functionality.