Abstract :
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5D- and 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die interconnects contain TSVs. Both 2.5D- and 3D-SICs are fraught with test challenges, for which solutions are only emerging. In this paper, we classify the test challenges as (1) test flows, (2) test contents, and (3) test access.
Keywords :
elemental semiconductors; integrated circuit interconnections; integrated circuit testing; silicon; three-dimensional integrated circuits; 2.5D-SIC; 3D-SIC; Si; TSV-based 2.5D-stacked IC testing; TSV-based 3D-stacked IC testing; interdie interconnects; passive silicon interposer base; stacked active dies; test access; test contents; test flows; thinned-down wafer substrate; through-silicon vias; Circuit faults; Integrated circuit interconnections; Probes; Stacking; Testing; Three dimensional displays; Through-silicon vias;
