High performance 0.25 μm SRAM technology with tungsten interpoly plug

A high performance 0.25 μm CMOS process has been developed for fast static RAMs, featuring retrograde wells, shallow trench isolation with 0.55 μm active pitch, a 55 Å nitrided gate oxide, 0.25 μm polycide gate surface channel NMOS and PMOS transistors with drive currents of 630 and 300 μA/μm respectively at an off-leakage of 10 pA/μm, overgated TFTs with an on/off ratio greater than 6·10 ⁵, stacked capacitors for improved SER, five levels of polysilicon planarized by chemical-mechanical polishing (CMP), with two self-aligned interpoly contacts and a tungsten interpoly plug (WIP) that connects 3 poly layers without parasitic diodes, 0.35 μm contacts and a 0.625 μm metal pitch. A split word-line bitcell was scaled to an area of 3.74 μm² using 0.25 μm design rules