Title :
Prototyping implementation for low-complexity real-time MPEG-2 variable length encoder
Author :
Hsia, Shih-Chang
Author_Institution :
Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol., Taiwan
Abstract :
MPEG-2 coder has become a standard core for video compression, and the whole module of variable length code (VLC) is a key component within MPEG-2 system. In this study, a real-time VLC encoder is developed by using discrete logic architecture rather than memory-based. In order to improve the chip efficiency, the codeword bank is constructed by order of codeword consisting of tri-state buffer. Three main VLC codeword tables for MPEG-2 system involved coded block pattern, motion vector and DCT coefficients all are efficiently realized in this work. The prototyping circuit is successfully implemented by using Verilog high-level description language and then fitted into a FPGA chip. The total gate-count can be reduced about 30% compared to the conventional VLC designs.
Keywords :
VLSI; data compression; field programmable gate arrays; hardware description languages; integrated circuit design; video coding; DCT coefficients; FPGA chip; MPEG-2 variable length encoder; VLC; VLC design; Verilog HDL; coded block pattern; codeword bank; discrete logic architecture; motion vector; prototyping circuit implementation; real-time VLC encoder; tri-state buffer; variable length code; video compression; Circuits; Code standards; Discrete cosine transforms; Field programmable gate arrays; Hardware design languages; Logic; Memory architecture; Prototypes; Transform coding; Video compression;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
DOI :
10.1109/IWSOC.2003.1213067
