A gate-level timing model for SOI circuits

Partially depleted floating-body (PDFB) SOI technology offers the potential of increased speed and lower power dissipation over traditional bulk CMOS. A key problem, however, related to the use of traditional design flows for new SOI designs is that the delay of logic gates built of PDFB SOI transistors varies according to the signal history. This presents a complication for implementing timing analysis or simulation of logic circuits. In this paper, we have formulated a simulation model that allows one to track the changes in delay during a dynamic gate-level simulation of the PDFB SOI circuit. This is essential in order to properly account for the shift of transistor body voltage in SOI devices. The model captures the "state" of a logic gate via two delay "state variables" which represent the rise and fall delay of the logic gate. As the logic circuit is simulated, state variables become updated