Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm

A new algorithm for one-dimensional (1-D) median filter has been presented recently (A.A.Hiasat et al., 1999). The algorithm uses the majority concept in determining the bits of the median value. In this paper, we are proposing a new hardware structure for the algorithm, which is more efficient than the structure proposed previously. This (1-D) filter is extended to a two-dimensional (2-D) separable median filter. A hardware implementation the 2-D filter is, also, proposed. A semi-custom VLSI implementation of the proposed 2-D separable median filter architecture, of a (3×3) window, has been fabricated on silicon using 2 μm CMOS technology. Testing results are reported