Modular architecture for a family of multilevel 256/192/128/64 Mbit 2-bit/cell 3 V-only NOR flash memory devices

Author

Silvagni, Andrea ; Zanardi, Stefano ; Manstretta, Alessandro ; Scotti, Marco ; Crippa, Luca ; Ragone, Giancarlo ; Fusillo, Giuseppe ; Campardo, Giovanni ; Khouri, Osama ; Stefanelli, Marcello

Author_Institution

Memory Product Group, STMicroclectronics, Milan, Italy

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

937

Abstract

This paper presents a family of 2 b/cell devices fabricated in 0.15 μm STI CMOS technology NOR-type flash memory. The device organization is based on a modular architecture that allows a very fast generation of all devices of the family from 64 Mbit to 256 Mbit having very similar performance. The modular architecture mainly concerns read path and high Voltage management aspects. A very realistic chip emulation of all devices is possible by using the 256 Mbit parent chip. The 256 Mbit device has 90 mm² die size and it is composed of 256 1-Mbit sectors with hierarchical row and column decoding. Asynchronous access time with error correction is 120 ns for the 256 Mbit. Burst mode read at 50 and 66 MHz is also available

Keywords

CMOS memory circuits; NOR circuits; PLD programming; flash memories; memory architecture; 0.15 micron; 120 ns; 50 MHz; 64 to 256 Mbit; 66 MHz; HV management aspects; STI CMOS technology; error correction; hierarchical column decoding; hierarchical row decoding; high voltage handling; modular architecture; multilevel NOR flash memory devices; programming; CMOS technology; Circuits; Decoding; Emulation; Error correction; Error correction codes; Flash memory; Silicon; Throughput; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957627

Filename

957627