ESD test methods on integrated circuits: an overview

Author

Ker, Ming-Dou ; Peng, Jeng-Jie ; Jiang, Hsin-Chin

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Taiwan

Volume

2

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

1011

Abstract

ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by certain organizations, such as ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. There are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) pin-to-VSS, (2) pin-to-VDD, (3) pin-to-pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit testing; production testing; standards; 1 kV; 2 kV; 200 V; AEC; CDM; EIA/JEDEC; ESD immunity; ESD stresses; ESDA; HBM; IC products; MIL-STD; MM; SDM; deep-submicron CMOS; industrial standards; pin combinations; sample size; test methods; test standards; zap interval; zap number; CMOS integrated circuits; CMOS technology; Circuit testing; Electrostatic discharge; Integrated circuit technology; Integrated circuit testing; Pins; Semiconductor device modeling; Standards development; Standards organizations;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957647

Filename

957647