DocumentCode
1660397
Title
Delay-sensitive power estimation at the register-transfer level
Author
Bruni, D. ; Olivieri, G. ; Bogliolo, A. ; Benini, L.
Author_Institution
Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
Volume
2
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
1031
Abstract
Zero-delay estimates of RTL power tend to underestimate power consumption because they neglect spurious transitions due to unequal propagation delays. We propose a new RTL power estimation flow that accounts for these phenomena. Experiments show that zero-delay analysis may grossly underestimate power, and that the proposed techniques achieve superior accuracy and robustness
Keywords
delay estimation; high level synthesis; logic simulation; table lookup; RTL design; RTL power estimation flow; delay-sensitive power estimation; look up table model; register-transfer level; robustness; spurious transitions; unequal propagation delays; Circuit simulation; Clocks; Computational modeling; Data mining; Delay estimation; Energy consumption; Propagation delay; Robustness; Sampling methods; Tellurium;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN
0-7803-7057-0
Type
conf
DOI
10.1109/ICECS.2001.957656
Filename
957656
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