DocumentCode
1661080
Title
Response compaction for test time and test pins reduction based on advanced convolutional codes
Author
Han, Yinhe ; Hu, Yu ; Li, Huawei ; Li, Xiaowei ; Chandra, Anshuman
Author_Institution
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
fYear
2004
Firstpage
298
Lastpage
305
Abstract
This paper addresses the problem of test response compaction. In order to maximize compaction ratio, a single-output encoder based on check matrix of a (n, n-1, m, 3) convolutional code is presented. When the proposed four theorems are satisfied, the encoder can avoid two and any odd erroneous bit cancellations, handle one unknown bit (X bit) and diagnose one erroneous bit. Two types of encoders are proposed to implement the check matrix of the convolutional code. A large number of X bits can be tolerated by choosing a proper memory size and weight of check matrix, which can also be obtained by an optimized input assignment algorithm. Some experimental results would verify the efficiency of the proposed optimized algorithm.
Keywords
convolutional codes; error analysis; integrated circuit design; integrated circuit testing; signal processing; test equipment; check matrix based single-output encoder; check matrix weight; compaction ratio; convolutional codes; erroneous bit cancellations; erroneous bit diagnosis; memory size; optimized input assignment algorithm; test pins reduction; test response compaction; test time reduction; unknown bit handling; Block codes; Circuits; Compaction; Computers; Convolutional codes; Error correction codes; Linear code; Pins; Polynomials; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on
ISSN
1550-5774
Print_ISBN
0-7695-2241-6
Type
conf
DOI
10.1109/DFTVS.2004.1347852
Filename
1347852
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