An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits

Author

Paulus, Christian ; Brederlow, Ralf ; Kleine, Ulrich ; Thewes, Roland

Author_Institution

Corporate Res., Infineon Technol., Munich, Germany

Volume

1

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

107

Abstract

A new method is presented which allows us to optimize active device area in complex mismatch- and 1/f-noise-sensitive analog integrated circuits. The method is based on a fully analytical approach and represents an efficient alternative to time consuming Monte-Carlo simulations and numerical iteration procedures. Moreover, it allows us to estimate total chip areas required to guarantee matching and noise performance with a high precision. The method is suitable for integration in the design flow of mixed signal circuits

Keywords

1/f noise; analogue integrated circuits; circuit CAD; circuit layout CAD; circuit optimisation; flicker noise; integrated circuit design; integrated circuit layout; integrated circuit noise; minimisation; mixed analogue-digital integrated circuits; sensitivity analysis; 1/f-noise sensitive analog ICs; active device area optimisation; analog integrated circuits; area minimization procedure; matching; mismatch-sensitive analog ICs; mixed signal circuits; noise performance; precise design method; sensitivity analysis; total chip area estimation; Analog circuits; Bandwidth; Design methodology; Design optimization; Frequency; Integrated circuit technology; MOSFETs; Optimization methods; Resistors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on

Print_ISBN

0-7803-7057-0

Type

conf

DOI

10.1109/ICECS.2001.957687

Filename

957687