Toggle-masking for test-per-scan VLSI circuits

Author

Parimi, Nitin ; Sun, Xiaoling

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2004

Firstpage

332

Lastpage

338

Abstract

This paper presents a novel toggle-masking technique that eliminates the switching activity in a circuit under test (CUT) during the scan-shifting in a test-per-scan test. Conventional scannable D flip-flops (DFFs) are modified to ensure that CUT inputs remain unchanged until an entire test vector is loaded, significantly reducing the power dissipation in the CUT. Our experiments on ISCAS85/89 benchmark circuits show that the proposed technique offers an average of 47% savings in average power compared to previous work (S. Gerstendorfer and H. Wunderlich, Proc. Int. Test Conf., pp. 77-84, 1999), and an average of 99% savings in average power and 8% savings in peak power with respect to test-per-scan circuits with conventional DFFs.

Keywords

VLSI; design for testability; flip-flops; integrated circuit testing; logic testing; low-power electronics; CUT inputs; DFF; ISCAS85189 benchmark circuits; average power savings; circuit under test; design for testability; peak power savings; power dissipation; scan-shifting; scannable D flip-flops; switching activity; test vector; test-per-scan VLSI circuits; test-per-scan test; toggle-masking; Circuit testing; Clocks; Design for testability; Energy consumption; Flip-flops; Floors; Power dissipation; Sun; Switching circuits; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on

ISSN

1550-5774

Print_ISBN

0-7695-2241-6

Type

conf

DOI

10.1109/DFTVS.2004.1347857

Filename

1347857