• DocumentCode
    1661255
  • Title

    Algorithms for interface timing verification

  • Author

    McMillan, Kenneth L. ; Dill, David L.

  • Author_Institution
    Sch. of Comput. Sci., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1992
  • Firstpage
    48
  • Lastpage
    51
  • Abstract
    Algorithms for analyzing systems of inequalities with min/max constraints that arise in interface timing specifications are examined. A general form of the inequality is shown to be NP-complete, but some interesting special cases can be solved efficiently. A branch-and-bound solution to the general case is developed and applied to a previously published example
  • Keywords
    computational complexity; logic design; minimax techniques; NP-complete; branch-and-bound solution; interface timing verification; min/max constraints; systems of inequalities; Algorithm design and analysis; Capacitive sensors; Computer science; Constraint optimization; Contracts; Delay effects; Digital circuits; Linear programming; Polynomials; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-3110-4
  • Type

    conf

  • DOI
    10.1109/ICCD.1992.276208
  • Filename
    276208
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1661255